1. Field of the Invention
This invention relates generally to processor-based systems, and, more particularly, to register caching in processor-based systems.
2. Description of the Related Art
Conventional processor-based systems typically include one or more processing elements such as a central processing unit (CPU), a graphical processing unit (GPU), an accelerated processing unit (APU), and the like. The processing units include one or more processor cores that are configured to access instructions and/or data that are stored in a main memory and then execute the instructions and/or manipulate the data. Each processor core includes a floating point unit that is used to perform mathematical operations on floating point numbers when required by the executed instructions. For example, conventional floating-point units are typically designed to carry out operations such as addition, subtraction, multiplication, division, and square root. Some systems can also perform various transcendental functions such as exponential or trigonometric calculations. Floating-point operations may be handled separately from integer operations on integer numbers. The floating-point unit may also have a set of dedicated floating-point registers for storing floating-point numbers.
Floating-point units can support multiple floating-point instruction sets. For example, the x86 architecture instruction set includes a floating-point related subset of instructions that is referred to as x87. The x87 instruction set includes instructions for basic floating point operations such as addition, subtraction and comparison, as well as for more complex numerical operations such as the tangent and arc-tangent functions. Floating-point instructions in the x87 instruction set can use a set of architected registers (conventionally known as MMX registers) that can be mapped to physical registers in the floating-point unit. For another example, computers that include multiple processing cores may support a single instruction, multiple data (SIMD) instruction set. The x86 architecture SIMD instruction set supports another floating-point related subset of instructions that are referred to as Streaming SIMD Extensions (SSE). Floating-point instructions in the SSE instruction set can use another set of architected registers (conventionally known as XMM registers) that can also be mapped to physical registers in the floating-point unit.
Different applications running on the processing unit can therefore use the x87 floating-point instruction set, the SSE floating-point instruction set, or a mixture of the two instruction sets. Consequently, architected registers for both instruction sets are mapped to physical registers in the floating-point unit so that both sets of architected registers are available to the applications running on the processing unit. Mapping architected registers for both instruction sets to physical registers in the floating-point unit consumes area on the chip, timing resources, and power. Depending on the instruction sets used by different applications, the resources that are allocated to the different types of instruction sets may not be used, thereby reducing the efficiency of the processing unit.